STEPPER
ONE PRIMITIVE · ONE EDGE PER BLOCK

A processor that steps with the chain.

2,161 NAND gates, 167 flip-flops and 256 bytes of RAM, composed from a single logic primitive and nothing else. The contract does not emulate the processor. It walks every gate, every block. Whoever pays for a step takes that step, and the byte they send is what the machine reads.

Run the processor → Open the launchpad → Read the datasheet
NAND gates2,161
Flip-flops167
Clock1 BLOCK
Switching now 0
§ 01 · THE MACHINE

Nothing here is a recording.

The netlist running in the console above is the same one a contract interprets on-chain: 2,161 NAND gates in topological order, then every flip-flop latching at once, with its RAM and its input port handled here exactly as the contract handles them.

The map above is the floorplan, not a chart. Seven regions, each with the area its block's gates actually take, and every square in them is one NAND lighting on the cycle it flipped. Run an add and the ALU lights; run a mov and the register file does while the ALU barely stirs.

ST-8 / GATE ARRAY CYCLE 0
Seven blocks · area is gate count · one square, one NAND
Cycle0
PC0x000
Out0
Flags··
Control
Clock rate
Program
IN port · your byte 0–255 · what the program reads with in
Uptime at current rate 0.0 s
Register file 16 × 8 bits
What it is made of

Seven blocks, standing like volumes on a shelf. Pull one out to see its framework and what it cost. The numbers are not estimates: they are what each block still weighed after the optimiser had finished with it, and together they are the 2,161.

Hover or tap a spine to open it

§ 02 · FABRICATION

From one gate to blockspace.

No synthesiser, and no netlist borrowed from anywhere. The processor is written as a program that places NAND gates, one at a time, and the table that reaches the chain is what that program emitted. You can run it yourself: npm run silicon.

Topological order costs nothing here. A gate can only name wires that already exist, so building in call order builds in dependency order, and the sort a synthesised netlist needs never has to happen.

Place, then prune

Seven towers, and the height of each is real. One per block of the processor, as tall as the gates that block actually carries. They rise in the order the placer emits them, and then the optimiser walks the row and every one of them settles: eleven gates in every hundred fold to a constant, duplicate something already on the die, or feed nothing at all.

being placed shipped optimised away
01

One primitive

Every adder, mux and decoder is composed from nand(a, b). Nothing else exists to build with, so the gate count is the honest cost.

02

The optimiser

Constants folded, repeated logic shared, double negations cancelled, gates nobody reads dropped. 2,425 placed, 2,161 shipped.

03

Four checks

The build refuses to write the netlist unless all four pass. Verification is not a step you can skip here, because nothing exists until it succeeds.

04

Gate table

The netlist becomes data, not code. Unrolling 2,161 gates would blow past the 24 kB contract ceiling.

05

The chain

step() reads ROM[pc], evaluates the cone, latches the flops, writes one slot.

Verification

Four checks, and none of them is the same check twice.

A test suite that checks a design against itself proves nothing. These four are deliberately different in kind, and the optimised netlist is the one they run against, because that is the one that ships.

Check 01

1,052,672 vectors

Every arithmetic and logic operation swept against plain arithmetic. Every operand, both carry states, gates driven directly into states no program would reach.

Check 02

An independent model

The same instruction set written the ordinary way, in + and &. It exists to disagree with the gates. If it ever does, the build stops.

Check 03

The shipped path

Check 02 again, but run through the exact simulator your browser loaded to draw the die map above. Not a copy of it.

Check 04

Liveness

The mainnet program must survive 20,000 cycles of random input without halting. The self-test must halt, having passed.

Check 05 · the contract itself. The four above prove the netlist. They cannot prove that the assembly walking it compiles the way it reads, so npm run evm puts the compiled contracts into an EVM and runs the processor through them. After every single block it compares the chip's cycle, program counter, output port, both flags, the halt bit and all sixteen registers against an independent model, then reads all 256 RAM cells back and compares those.

It does that twice: once for the ST-8, and once for the ST-16 that does not ship until R2. 11,216 bytes of the 24,576-byte ceiling for the ST-8 gate array, 18,339 for the ST-16. The output column of the gate table is not stored at all, because a gate can only name wires that already exist, so gate k always drives net 210 + k.
§ 03 · INSTRUCTION SET

Five bits. Thirty-two opcodes.

The opcode field is five bits wide, so thirty-two is not a design choice: it is arithmetic. Every one of them is now used. Widening the field would mean taking a bit back from the immediate, and that is a decision for a wider generation rather than this one.

25-bit words. Sixteen registers of eight bits, a 10-bit program counter, 1,024 words of ROM and 256 bytes of RAM. Every instruction completes in one block except ld, which takes two honest cycles because the address has to latch before the data can come back.

Word format: [24:20] op · [19:16] rd · [15:12] rs · [11:0] imm/addr

Lit as the processor uses them ·
OpMnemonicEffectFlags
The last three cost sixty-five gates between them. The decoder already emitted all thirty-two one-hot lines, so the slots were paid for and only the logic reading them was not. tst rides the AND the way cmp rides the adder: it computes a result so the flags are right, then declines to keep it. swap is a permutation of the wires, like the shifts, and no gate computes anything. jmpr is the one that changes what can be written rather than how tidily: an address in a register is a jump table, a dispatch loop, and a return address you can hold.

nand is in the set because it is the only primitive the die is built from. Everything else here is composed out of it, so the one instruction that is not composed of anything is the one worth naming.
§ 04 · THE CLOCK

Anyone can expose the next field.

In a fab, a stepper exposes a wafer one field at a time and the fab decides when. Ours has no fab. step(uint256) carries no owner check, no keeper, no schedule and no queue: a chip is its own contract, so there is nothing to be listed in and nobody to ask. You call the processor at the address it lives at, and the field is exposed. Whoever paid is written into the event as that cycle's sponsor, permanently.

What is missing is what makes it work. Every edge emits a fixed share of the chip's reserve and costs a fixed amount of gas, so the processor advances exactly as fast as those two numbers say it should and not one block faster. Nobody schedules it, nobody can stop it, and nobody has to be trusted to keep it alive. If an edge is worth more than it costs, somebody takes it. If it is not, the machine stands still until it is — which is an answer, not a failure.

Power a chip ···

One step, one block, one cycle. Whoever sends it pays the gas and earns that cycle's share of the chip's token.

Byte Rides along with your step. It is what the program reads with in.
Anyone may take a step once the clock starts at T-0.
Specification Read from the netlist
What a cycle pays ·
Emission is arithmetic; gas is measured. Neither is a forecast.
These are measured, not estimated. They come from npm run evm, which deploys the contracts into a real EVM and runs the processor through them, and the deploy figures are what chain 4663 itself quotes for the real bytecode. Numbers nobody ran are just decoration.
§ 05 · THE FACTORY

Mint your own processor.

Every chip is an NFT and a real 8-bit machine: your program in its ROM, 256 bytes of RAM, executing on-chain one cycle per block, and its own token, whose reserve leaves one clock cycle at a time, to whoever keeps the processor alive.

Apart from buying them, that is the only way to obtain a chip's tokens. There is no second path, and no mint function anywhere: supply is fixed at birth and nobody can print more. Not the operator, not the chip's owner, not the factory.

THE LAUNCHPAD

Write the program. Run it on the gates. Then mint it.

A separate page with an assembler, a live die and the specification plate for the chip you are describing. It costs nothing, needs no wallet, and the processor it runs your program on is the real one.

Open the launchpad →
Assembler

Thirty-two instructions, checked

The workbench reads its opcode numbers straight out of the netlist, so it cannot assemble an instruction the silicon does not have, and cannot miss one it does. Errors carry a line number and say what was expected.

Silicon

Your program on 2,161 gates

Press assemble and the program loads into a live machine on the page. What lights up is the propagation through the cone, cycle by cycle, exactly as a contract would walk it.

Analysis

Does it stop?

A chip that halts earns nobody anything until its owner restarts it. The launchpad follows both sides of every branch and tells you which kind you wrote, before the question costs money.

§ 06 · THE POINT

Compute you can re-execute.

A chain does not replace silicon. It runs on silicon, N times over. Every cycle this processor executes is executed again by every validator, so on-chain compute is not an alternative to a datacenter: it is a datacenter multiplied by the size of the validator set. Anybody selling a chain that replaces GPUs is selling a thermodynamics that does not exist.

Redundancy is the cost. What it buys is a property no amount of silicon can produce on its own.

A chip in a datacenter cannot prove what it did. A model answers, a job returns a number, and the only thing backing it is that somebody says so. This processor is deterministic, its whole history is on chain, and any one of its cycles can be replayed by anybody, forever, from the gate table up. The interesting question was never how fast it computed. It is whether the answer can be checked without asking permission.
One computation, executed by everyone

A result travels a closed circuit. Every node it reaches re-executes the same cycle and stands up, and nothing counts until it has come all the way round. Then the whole ring latches at once and the spokes draw in.

That last frame is the argument of this section. Not that it computed quickly — it did not — but that everybody got the same answer and anyone can check.

Now

A live processor

Every cycle paid for, signed and engraved. A machine whose entire history, every byte it was ever fed, is auditable down to the gate.

Next

Compose and batch

Many cycles per transaction, chips wired into chips, and a neural network synthesised to NAND: inference running gate-level inside the chain.

Goal

The verifiable co-processor

The processor runs off-chain at full speed. The result is posted with a bond. A dispute bisects to the single contested cycle and replays it inside the gate array. The chain stops being the engine and becomes the court.

§ 07 · THE INSTRUMENT

There is nothing behind this page.

A site about a processor that needs a backend to show you the processor is making a claim it cannot keep. Everything here runs in your tab: the netlist, the machine, the assembler, the halt analysis. Disconnect after it loads and the processor keeps stepping.

The one thing our host does is hand you files. No database, no API, no session, no server-side rendering and no analytics. There is nothing back there that could lie to you about the die, because the die is computed on your machine out of a table you already have.

Run it somewhere that isn't here
Cold load, measured CACHE DISABLED
Counted off the wire, not estimated
Per second, in your tab
20,960

Gate evaluations, at the console's default ten cycles a second. Every one of them is a real NAND being computed, not a frame of animation.

Per build, on ours
1,052,672

Exhaustive vectors through the combinational cone, plus a twenty-thousand-cycle differential run. The build refuses to write a byte unless all four checks pass.

Where it is hosted is deliberately boring. A single Node process serving static files, behind a CDN, with ETags so a repeat visit revalidates instead of re-downloading. It could be replaced with any file host tomorrow and nothing about the processor would change, which is the point of saying so.
§ 08 · ROADMAP

Shipped, building, and next.

Every release is one of two things: software wrapped around contracts that cannot change, or a new generation of silicon that has to pass the same proofs the current one did before it is allowed to exist. One token carries through all of it. There is no v2 and no migration, because the contracts holding the silicon are pure and ownerless and new generations are added beside them rather than over them.

Every line inside is a deliverable, not a theme, and the markers are the point. A filled one exists today and you can run the command that proves it. An open one does not exist, and nothing on this page pretends otherwise.

T-0The processor
R1The launchpad
R2Wider silicon
R3The court
R4Silicon for AI
Five releases · one open
T-0

The processor goes live

IN BUILD

One chip, one program, one clock nobody owns. No token, no launchpad and nothing to buy: the only claim at T-0 is that a real gate-level processor executes inside a contract and that anybody can advance it. Everything below except the last line is done and has a command that proves it.

  • 2,161-gate NAND netlist, placed one gate at a time by our own program
  • Four checks in the build, which refuses to emit a netlist unless all four pass
  • A fifth in a real EVM: the compiled contracts, run and compared per block
  • 1,052,672 exhaustive vectors across 21 operations, every operand, both carries
  • The same netlist running in your browser, gate for gate
  • The workbench: assembler, live die, halt analysis, all of it free
  • A full opcode field: thirty-two instructions, tst, swap and jmpr included
  • IGateArray and a generation-agnostic Chip, one bytecode for both widths
  • Compiled, deployed into a real EVM and compared block by block against an independent model
  • A transient reentrancy guard, added before deployment rather than after
  • Gas measured, not estimated: 2.2M to deploy the silicon, 380k a cycle
  • A testnet rehearsal path on chain 46630, at a fortieth of the price
  • Chip #1 deployed, and step() open to anybody who pays for it
R1

The launchpad opens

NO CONTRACT CHANGES

Minting from the browser. The gate array deployed at T-0 does not move: every chip minted here points at that same pure, ownerless contract, so R1 adds software around silicon that is already fixed.

  • Mint from the workbench: your name, your ticker, your program
  • A per-chip token, one billion units, and no mint function anywhere in it
  • The mining reserve, paid one cycle at a time to whoever sponsors the step
  • An on-chain renderer: the specification plate drawn as SVG by the contract itself
  • An MCP server, so an agent can mint, sponsor and read a chip with no browser at all
  • A public index of every chip, its program, and who has been paying for its cycles
R2

Wider silicon

ST-16 ALREADY BUILDS

A wider machine is a build flag rather than a rewrite, and the contract for it already exists: ST16GateArray compiles, fits the ceiling and passes the same EVM proof the ST-8 does, through the same interface. What is left is the console, which draws eight lights and holds RAM as bytes, and the gas to carry twice the gates.

  • ST-16: 3,787 gates and 311 flip-flops, out of the same builder and the same source
  • ST-16 compiled and proved in an EVM, through the same interface as the ST-8
  • One Chip contract, byte for byte identical, running both generations
  • The instruction set widened once and both generations got it, because there is one description
  • ST-16 on-chain, with a 16-bit datapath and a 64 KB address space
  • ST-32 after it, and the same four proofs before either ships
  • Batched cycles: one transaction that advances many edges instead of one
  • Every generation is new silicon beside the old, never a rug under it
R3

The court

FIRST PROTOCOL UPGRADE

The gate array is already a referee that anybody can appeal to, which is the part most people miss. A processor that can be replayed cycle by cycle inside a contract is exactly the thing a fraud proof needs at the bottom of it.

  • Run the processor off-chain at full speed and post the result with a bond
  • A challenge bisects the disputed run down to one contested cycle
  • That single cycle is replayed inside the deployed gate array, which settles it
  • Off-chain speed with on-chain truth: the chain stops being the engine and becomes the court
R4

Silicon for AI

RESEARCH

The builder that placed this processor does not know it is a processor. It places NAND gates from a program, and a small neural network is also a program that can be placed from NAND.

  • A quantised network synthesised to NAND by the same placer, and checked the same way
  • Inference running gate-level inside the chain, and through the court at real speed
  • The first inference anybody can re-execute, cycle for cycle, forever
None of this needs a new token, and none of it can force one. The contracts holding the silicon are pure and ownerless: there is no address that can pause them, upgrade them or take them away, which is exactly why a later generation has to be built beside them rather than over them. One token carries through every release above. No migration, no v2, no snapshot, because there is no mechanism by which there could be.
§ 09 · THE NAME

Why Stepper.

Names in this industry usually promise a result. This one names a motion, because the motion is the only thing we are certain of.

A clock edge, stepping. Halfway through the sweep the plate is the mark in the corner.

In a fab, the stepper is the machine that prints a die. It does not expose the whole wafer at once, because no lens is that good. It exposes one field, moves, exposes the next, and keeps going until the wafer is written. The picture above is that machine mid-pass: the bright square is the field under the lens right now, the ones behind it are already printed, and the rest are still blank silicon.

Here the word means something narrower and far more literal. step() is a function. One call, one clock edge, one field of the wafer. The chain closes a block and the processor advances exactly once, and it does that because somebody decided it was worth the gas.

The three drawings are the same drawing. A clock edge crosses a gate. The same edge crosses a die, which is what the console above is showing you and what the mark in the corner is a picture of. And a stepper crosses a wafer, which is where the name came from. Nothing about that is a metaphor we reached for afterwards. The processor is built out of one primitive, arranged in fifty-five levels of depth, and a signal genuinely does arrive at the far side one level at a time.

There is a second reason the word fits, and it is the one that matters commercially. Nobody owns the stepper. In a fab the machine belongs to whoever bought it. Here it belongs to whoever pays for the next exposure. There is no keeper, no schedule and no privileged caller: the processor advances when the market decides a cycle is worth more than the gas it costs, and stalls when it is not.

That is the honest limit of the name, so it is worth saying plainly. Stepper does not promise speed. It does not promise intelligence and it does not promise that a chain can do a datacenter's job. It promises a machine that takes one step at a time, in public, where anybody can check the step it took.

The chain closes a block. The stepper takes a step. That is the whole mechanism, and everything else on this page is a consequence of it.

STEPPER · ST-8 · one block, one step